1. Field of the Invention
The present invention relates to a clock distribution circuit for use in semiconductor integrated circuits and the like, and more particularly to a clock distribution circuit with reduced clock skew.
2. Description of the Related Art
Recently, large-scale integrated circuits (LSIs) have increased rapidly in clock frequency, and the fastest ones have reached a frequency as high as 1 GHz. An increase in clock frequency can immediately improve the performance of LSIs since clock synchronous circuits are the most common in LSI design at present. Thus, increasing clock frequency is a technique of great significance. LSIs in use for conventional computers and the like have various configurations which have been proposed for distributing a clock to clock reference terminals with reduced phase differences thereamong. Those in common use are, for example, clock distribution circuits of tree structure and clock distribution circuits of mesh type. Clock distribution circuits of tree structure are described in Japanese Patent Application Laid-Open Nos. Hei 5-233092 and Hei 9-307069. Clock distribution circuits of mesh type are disclosed in Japanese Patent Application Laid-Open No. Hei 6-244282.
FIG. 1 is a circuit diagram showing a conventional clock distribution circuit of tree structure. The conventional tree-structured clock distribution circuit has an LSI chip 702 provided with an input terminal 701 through which a clock signal is input. The input terminal 701 is connected with inverters 703 through 705 in series. The inverter 705 in turn is connected with clock distribution wirings 712L and 712R having the same length and the same width. The clock distribution wiring 712R is connected with inverters 706a and 706b at its end. The clock distribution wiring 712L is connected with inverters 706c and 706d at its end. The inverters 706a-706d in turn are provided with wirings having the same length and the same width, being connected with a plurality of inverters 707a and 708a-708d, inverters 707b and 710a-710d, inverters 707c and 709a-709d, and inverters 707d and 711a-711d, respectively.
In the conventional clock distribution circuit configured thus, each wiring is formed in the same length and the same width which reduces the clock skew of the clocks arriving at the ends. A plurality of isometric wirings are also used from the buffers at the ends of the tree to a plurality of terminals for clock reference to reduce the clock skew. The clock distribution circuit described in Japanese Patent Application Laid-Open No. Hei 5-233092 mentioned above is of such configuration.
Meanwhile, the conventional clock distribution circuit described in Japanese Patent Application Laid-Open No. Hei 9-307069 mentioned above includes delay buffers to adjust the wiring delay at each node of the clock tree. Such configuration puts each stage of the clock tree into the same phase.
FIG. 2 is a circuit diagram showing a conventional clock distribution circuit of mesh type. The conventional mesh-type clock distribution circuit has an LSI chip 802 which is defined into a plurality of blocks 801. Each of the blocks 801 contains wirings 806 in the form of cross-meshes. The chip 802 is further provided with a buffer 804 for distributing a clock signal to the plurality of blocks 801 as a clock driver. In addition, clock distribution wirings 803 having the same length and the same width are provided from the buffer 804 to each of the blocks 801.
In the conventional clock distribution circuit configured thus, the use of mesh-form wirings produces smaller wiring resistances since the resistances can be regarded as parallel resistances. This allows the clock signals on lattice points to vary in voltage with a timing difference as small as negligible. The clock distribution circuit described in Japanese Patent Application Laid-Open No. Hei 6-244282 mentioned above is of such configuration.
Other types of clock distribution circuits include those described in Japanese Patent Application Laid-Open No. Hei 6-282350, which have LSIs containing a plurality of intra-block distribution circuits that utilize phase locked loops (PLLs), delay locked loops (DLLs), or the like having variable delay adjusters and phase comparators.
In the conventional clock distribution circuit described in the publication, the PLLS, DLLS, or the like always make comparisons and adjustments on mutual phases, so as to supply clocks in phase through clock reference terminals. According to this circuit, clocks can be distributed to the ends in phase even in the cases where the clock distribution wirings differ from each other in capacitance.
There have also been disclosed clock distribution circuits in which frequency multipliers using a variable delay adjuster are placed on the node portions of the clock tree (Japanese Patent Application Laid-Open No. Hei 7-253825). In the conventional clock distribution circuits, an external clock is multiplied inside to produce a higher clock.
These clock distribution circuits have been designed on the assumption that each clock wiring has a resistance component and a capacitance component. In this connection, a clock distribution circuit designed should be verified whether or not it satisfies the allowable value of clock skew, using a circuit modeling technique in which the rising time of a clock is obtained from the product of the load capacitance and the resistance component of the wiring. If the allowable value is satisfied, then the design is realized into circuitry.
xe2x80x9cIBM Journal of Research and Development vol. 39, No.5xe2x80x9d 9 (1995), pp.547-566, describes, however, the following points on microprocessors operating at a frequency of 300 MHz. That is, for a 1-cm-length wiring, the propagation delay time of the wiring is 130 through 370 pico-seconds; the rising time of propagated signals ranges from 100 to 900 pico-seconds; and the propagation delay time is not negligible with respect to the rising and falling times of the signals. It also reads that under these circumstances wirings must not be considered as RC distributed constant circuits in consideration of capacitance components and resistance components alone, but as transmission lines which further takes inductance into account.
Meantime, the clock distribution circuits described in the above-cited publications were designed in terms of RC distributed constant circuits. This produces a problem with high-frequency operations.
For example, the conventional clock distribution circuits described in Japanese Patent Application Laid-Open Nos. Hei 5-233092 and Hei 6-244282 are all under the assumption that the propagation characteristics of signals will be determined only by resistance components and capacitance components. This precludes the proper operation of the circuits on the condition that the rising time of the clock approaches the signal propagation time of the signal lines and that their inductance components are not negligible. In the cases where the rising time of the clock is e.g. 10% the clock frequency, inductance becomes not negligible at frequencies above 300 MHz since the propagation time of the signal lines is in the range of 130 and 370 pico-seconds for each 1-cm wiring.
Moreover, the circuits described in Japanese Patent Application Laid-Open No. Hei 6-282350 with PLLs, DLLs or the like using variable delay adjusters and phase comparators become extremely hard to construct at frequencies e.g. above 1 GHz. For example, xe2x80x9cIEEE International Solid-State Circuits Conferencexe2x80x9d 2 (1997), pp.330-331, describes a technique in which a PLL itself has a jitter of 154 pico-seconds. When the PLL is mounted on an LSI, the jitter even increases because of uncertain factors such as source noise. The aforesaid literature, pp.332-333, describes another technique in which a DLL itself has a jitter as small as 68 pico-seconds; however, the jitter increases up to 400 pico-seconds when source noise of 1 MHz is applied. As seen above, the PLLs and DLLs are so strongly affected by electrical, uncertain factors such as source noise that they cannot be maintained below approximately 100 pico-seconds in jitter when mounted on an LSI. Consequently, the clock distribution circuits which carry out phase adjustment by using PLLs and DLLs and whose clock skew allowable is not greater than about 10% of the clock frequency will fail to distribute clocks when the clock frequency exceeds 1 GHz.
Moreover, the conventional clock distribution circuits described above have been designed as RC distributed constant circuits, and therefore are susceptible to device production variations. The effect of the device production variations extends to transistors generating variations in their output resistances (ON-state currents). This may be regarded as a phenomenon resulting from a change in the supply voltage to the same transistors. That is, in a line between two inverters, the device variation characteristics of the clock skew can be represented by the amount of the difference in signal""s propagation delay time produced by a change in the supply voltage to the transistor. The literature xe2x80x9cIEEE Transactions on Electron Devices, pp.118-124, January, 1993xe2x80x9d describes an equation to obtain a propagation delay time Tpd in an RC distributed constant circuit, which is shown in the equation (1) as follows:
Tpd=0.38xc3x97Rintxc3x97Cintxc3x97L2+0.69xc3x97(Rtrxc3x97Cintxc3x97L+Rintxc3x97CLxc3x97L+Rtrxc3x97CL)xe2x80x83xe2x80x83(1)
Here, Rint is the resistance of the wiring per unit length, Cint is the capacitance of the wiring per unit length, CL is the load capacitance of the wiring, and Rtr is the output resistance of the buffer.
The equation (1) to obtain a propagation delay time Tpd contains the output resistance Rtr of the transistor. This shows that the propagation delay time of the wiring designed as an RC distributed constant circuit depends on the device variations of the transistor. Accordingly, clock distribution circuits designed thus have a problem of causing variations in clock skew.
Furthermore, Japanese Patent Application Laid-Open No. Hei 9-51207 discloses microstrip transmission line substrates which can control wiring length to reduce a difference in absolute delay time. Application of such conventional transmission line substrates to clock distribution circuits, however, cannot efficiently suppress clock skew in high-frequency clock signals.
In view of the foregoing, an object of the present invention is to provide a clock distribution circuit which can distribute clock signals, particularly high-frequency clock signals, with smaller clock skew.
According to one aspect of the present invention, a clock distribution circuit comprises a plurality of blocks each having a plurality of circuits, a first clock driver which distributes a clock signal to each of the blocks, and second clock drivers each provided in one of the blocks. Each of second clock drivers distributes the clock signal to each of the circuits in the block. A first wiring is connected between the first clock driver and each of the second clock drivers so that the clock signal arrives at each of the second clock drivers in the same phase. A plurality of second wirings are connected between the second clock drivers and each of the circuits in the block. The second wirings may consist of transmission lines. The second wirings have a maximum length equal to or smaller than a product of clock skew allowable and a propagation velocity of an electromagnetic wave propagating through the second wirings.
According to another aspect of the present invention, a clock distribution circuit comprises a plurality of blocks each having a plurality of circuits, a plurality of first clock drivers each of which supplies a clock signal to each of the blocks, and second clock drivers each provided in one of the blocks. Each of second clock drivers distributes the clock signal to each of the circuits in the block. A plurality of first wirings are connected between the first clock driver and the second clock driver in each of said blocks so that the clock signal arrives at the second clock drivers in the same phase. A plurality of second wirings are connected between the second clock drivers and each of the circuits in the block. The second wirings may consist of transmission lines. The second wirings have a maximum length equal to or smaller than a product of clock skew allowable and a propagation velocity of an electromagnetic wave propagating through the second wirings.
In the present invention, the second wirings may consist of transmission lines whose maximum length is appropriately defined. This reduces clock skew to allow accurate distribution of clock signals at higher frequencies, and reduces the effect of device variations as well.
In other words, the wiring structure is decided in consideration of the effect of clock skew and inductance, so that high-frequency clock signals can be distributed to each circuit with smaller clock skew. In the conventional clock distribution circuits, variations in wiring delay time depend on the output resistances of transistors and the wiring resistances to cause the high susceptibility to device variations. In contract, the present invention uses transmission lines for the intra-block wirings, so as to be less subject to device variations of LSIs. The reason for this is that: the conventional circuits are affected by device variations in both wiring delay time and buffer delay time; meanwhile, in the present invention, the variations in wiring delay time are determined only by the propagation velocity of electromagnetic waves and the wiring length, which can eliminate the dependence on the performance of driven transistors to allow exclusive influence of the buffer delay time among the device variations.
The nature, principle and utility of the invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings in which like parts are designated by like reference numerals or characters.